Frequency synthesizers are circuits that take one or more input signals with known frequencies and produce one or more output signals at other frequencies. In most cases, frequency synthesizers accept one or more low frequency precise reference signals as inputs and generate a range of higher frequency signals that are mathematically related to the frequencies of the reference signals. Frequency synthesizers are found in virtually all modern communication systems, including wireless data networks, cellular phones, radio and televisions receivers, and fiber optic transceivers. Frequency synthesizers are not just found in communication systems, however, as they are also used as clock sources in other applications such as digital logic and radar systems.
One method of building frequency synthesizers uses phase-locked loops (PLLs). Common elements in most frequency synthesis PLLs include a tunable local oscillator circuit, phase detector, loop filter and frequency frequency reduction circuit. These elements are usually connected in a loop. The oscillator circuit is connected to the frequency synthesizer output and is, through a feedback mechanism, tuned to produce an output signal of the desired output frequency. The tuning is achieved by coupling the oscillator output signal through a frequency reduction circuit on the feedback path between the oscillator and the phase detector. The phase detector compares the frequency reduced oscillator signal and a precise reference frequency signal and generates an oscillator tuning signal that is coupled through the loop filter to the oscillator. In most frequency synthesizers, the feedback path frequency reduction is accomplished using a frequency divider.
A method using subsampling for frequency reduction in the feedback path was disclosed by Amr. N Hafez and Mohamed I. Elmasry in 2002 and 2003 in U.S. Pat. Nos. 6,463,112 and 6,614,866. The same authors provided further descriptions in A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers, published in the Proceedings of the 9th Great Lakes Symposium on VLSI, pages 306-309 in March of 1999 and in A Low Power Monolithic Subsampled Phase-Locked Loop Architecture for Wireless Transceivers, published in the Proceedings of the International Conference on Circuits and Systems (ISCAS), pages 549-552, volume 2, in July of 1999. The benefits of the subsampling method disclosed in these patents and publications are claimed to be reduced power consumption and improved phase-noise characteristics when compared to frequency divider based techniques. The subsampling design in said patent uses analog sample-and-hold circuits that perform a mixing operation between the oscillator signal and a sample signal of a precise frequency. With a sample signal that is below the Nyquist frequency of the oscillator signal, the analog sample-and-hold subsampling circuit output contains a low frequency alias of the oscillator signal which can be used by the phase detector in a manner similar to a frequency divided signal. The mixing operation by the analog sample-and-hold subsampling circuit, however, generates numerous low-frequency harmonic signals in addition to the desired low-frequency alias signal to be compared by the phase detector. These harmonic signals must therefore be attenuated through a secondary low-pass filtering method before the signal can be compared with the reference signal in the phase detector.
In a subsampling digitizer-based frequency synthesizer invention disclosed by George E. Von Dolteren in U.S. Pat. No. 6,603,362 the analog sample-and-hold circuit is replaced by an analog-to-digital converter (ADC). The ADC produces a digital output corresponding to the oscillator signal level, allowing digital processing of the subsampled signal.
In previous architectures relying on frequency reduction, the feedback path is the critical component in the PLL that limits the maximum frequency that can be generated by the frequency synthesizer. Complementary metal-oxide-semiconductor (CMOS) oscillators in the form of voltage-controlled oscillators (VCOs) have been demonstrated operating at frequencies well in excess of the unity-current gain frequency of a given CMOS process technology. An instance of such a VCO is described in the paper A 410 GHz CMOS push-push oscillator with an on chip patch antenna, by E. Seok et al. and was published in the Proceedings of the 2008 International Solid-State Circuits Conference, pages 472-474 on February 2008. Although using PLL-based frequency synthesizer for synthesis of signals at frequencies near or exceeding the unity-current gain frequency of a given process is desirable, development of PLL-based frequency synthesizers capable of achieving frequencies near or exceeding unity-current gain frequencies has been lagging. Frequency reduction in the feedback path using frequency divider or analog sample-and-hold subsampling methods have not been shown to be capable of operating at the required high frequencies. The digitizer approach to subsampling is even less likely to operate at the desired frequencies, as even the fastest documented ADCs operate at only a small fraction of the unity-current gain frequency of a given process technology.